ADTRG=ADTRG_0, REFSEL=REFSEL_0, OVWREN=OVWREN_0, AVGS=AVGS_0, ADLPC=ADLPC_0, ADIV=ADIV_0, ADSTS=ADSTS_0, ADLSMP=ADLSMP_0, ADHSC=ADHSC_0, MODE=MODE_0, ADICLK=ADICLK_0
Configuration register
| ADICLK | Input Clock Select 0 (ADICLK_0): IPG clock 1 (ADICLK_1): IPG clock divided by 2 3 (ADICLK_3): Asynchronous clock (ADACK) |
| MODE | Conversion Mode Selection 0 (MODE_0): 8-bit conversion 1 (MODE_1): 10-bit conversion 2 (MODE_2): 12-bit conversion |
| ADLSMP | Long Sample Time Configuration 0 (ADLSMP_0): Short sample mode. 1 (ADLSMP_1): Long sample mode. |
| ADIV | Clock Divide Select 0 (ADIV_0): Input clock 1 (ADIV_1): Input clock / 2 2 (ADIV_2): Input clock / 4 3 (ADIV_3): Input clock / 8 |
| ADLPC | Low-Power Configuration 0 (ADLPC_0): ADC hard block not in low power mode. 1 (ADLPC_1): ADC hard block in low power mode. |
| ADSTS | Defines the total sample time duration in number of full cycles 0 (ADSTS_0): Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b 1 (ADSTS_1): Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b 2 (ADSTS_2): Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b 3 (ADSTS_3): Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b |
| ADHSC | High Speed Configuration 0 (ADHSC_0): Normal conversion selected. 1 (ADHSC_1): High speed conversion selected. |
| REFSEL | Voltage Reference Selection 0 (REFSEL_0): Selects VREFH/VREFL as reference voltage. |
| ADTRG | Conversion Trigger Select 0 (ADTRG_0): Software trigger selected 1 (ADTRG_1): Hardware trigger selected |
| AVGS | Hardware Average select 0 (AVGS_0): 4 samples averaged 1 (AVGS_1): 8 samples averaged 2 (AVGS_2): 16 samples averaged 3 (AVGS_3): 32 samples averaged |
| OVWREN | Data Overwrite Enable 0 (OVWREN_0): Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. 1 (OVWREN_1): Enable the overwriting. |